Design Gateway IP Lock AES Encryption IP Security System
Design Gateway IP Lock AES Encryption IP Security System uses reliable Advanced Encryption Standard (AES) encryption technology, a common key cryptosystem chosen by NIST, US. Encryption and decryption are high-speed and AES is stronger than triple DES. AES is adopted with security for financial systems, LAN systems, and more. IP proprieties in the FPGA are protected from illegal copying by only including IP Lock and connecting with an encryption controller chip.
Features
- Strong security by AES encryption
- About 200msec cycle rate to change and encrypt authentication data
- Generate true random authentication data by natural random number generator
- Stop user logic when removing the chip
- Connecting I/O with FPGA are only 2 pins
- No need to input clock to IP Lock logic
- Provide easy "Laboratories Pack" and "IP Lock Writer + blank chip"
Block Diagram
Additional Resources
Videos
Publicado: 2017-05-22
| Actualizado: 2022-03-11