Texas Instruments AM62D Arm-Based Processors
Texas Instruments AM62D Arm-Based Processors are targeted for applications needing high-performance Digital Signal Processing. Key cores on the device include a C7000™ (“C7x”) scalar and vector DSP core from Texas Instruments and the Arm® Cortex®-A53, a dedicated Matrix Multiplication Accelerator (MMA), and an isolated MCU island. All are protected by industrial and automotive-grade safety and security hardware accelerators.
Along with the C7x DSP core, the AM62Dx SoC integrates up to quad Arm Cortex-A53, providing an additional 16.8KDMIPS compute and HLOS flexibility of Linux or a Real-Time Operating System (RTOS). Up to two Arm Cortex-R5F subsystems enable low-level, timing-critical processing tasks, leaving the Arm Cortex-A53 and DSP cores unencumbered for applications.
Integrated diagnostics and safety features support operations up to SIL-2 and ASIL-B levels, while the integrated security features protect data against modern-day attacks. The Texas Instruments AM62D device also offers a 3-port Gigabit Ethernet switch with Time-Sensitive Networking (TSN) to enable audio networking features such as Ethernet Audio Video Bridging (eAVB) and Dante. In contrast, peripherals like the McASP enable multichannel I2S and TDM Audio inputs and outputs.
Features
- Processor cores
- Up to quad Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
- Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with parity protection
- Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of the MCU channel with FFI
- 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- 512KB SRAM with SECDED ECC
- Single-core Arm Cortex-R5F at up to 800MHz, integrated to support device management with 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
- DSP with Matrix Multiplication Accelerator (MMA) based on single-core C7x
- C7x floating point, up to 40GFLOPS, 256-bit Vector DSP at 1.0GHz
- MMA up to 2TOPS (8b) at 1.0GHz
- 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with parity protection
- 1.25MB of L2 SRAM with SECDED ECC
- Up to quad Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
- Memory subsystem
- Up to 2.29MB of on-chip RAM
- 64KB of On-Chip RAM (OCRAM) with SECDED ECC can be divided into smaller banks in increments of 32KB for as many as two separate memory banks
- 256KB of On-Chip RAM with SECDED ECC in SMS subsystem
- 176KB of On-Chip RAM with SECDED ECC in SMS subsystem for TI security firmware
- 512KB of On-chip RAM with SECDED ECC in the Cortex-R5F MCU subsystem
- 64KB of On-chip RAM with SECDED ECC in the device/power manager subsystem
- 1.25MB of L2 SRAM with SECDED ECC in C7xDSP with MMA
- DDR Subsystem (DDRSS)
- Supports LPDDR4
- 32-bit data bus with inline ECC
- Supports speeds up to 3733MT/s
- Max addressable range of 8GBytes
- Up to 2.29MB of on-chip RAM
- Functional safety
- Functional safety-compliant targeted [automotive]
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 functional safety system design
- Systematic capability up to ASIL D targeted
- Hardware integrity up to ASIL B targeted
- Safety-related certification with ISO 26262 certification by TÜV SÜD planned
- AEC-Q100 qualified [automotive]
- Functional safety-compliant targeted [automotive]
- Security
- Secure boot supported
- Hardware-enforced Root-of-Trust (RoT)
- Support to switch RoT via backup key
- Support for takeover protection, IP protection, and anti-rollback protection
- Trusted Execution Environment (TEE) supported
- Arm TrustZone®-based TEE
- Extensive firewall support for isolation
- Secure watchdog/timer/IPC
- Secure storage support
- Replay Protected Memory Block (RPMB) support
- Dedicated security controller with user-programmable HSM core and dedicated security DMA and IPC subsystem for isolated processing
- Cryptographic acceleration supported
- Session-aware cryptographic engine with the ability to auto-switch key material based on the incoming data stream
- Supports cryptographic cores
- AES–128-/192-/256-Bit key sizes
- SHA2–224-/256-/384-/512-Bit key sizes
- DRBG with a true random number generator
- PKA (Public Key Accelerator) to assist in RSA/ECC processing for secure boot
- Session-aware cryptographic engine with the ability to auto-switch key material based on the incoming data stream
- Debugging security
- Secure software-controlled debug access
- Security-aware debugging
- Secure boot supported
- High-speed interfaces
- Integrated Ethernet switch supporting (total of two external ports)
- RMII(10/100) or RGMII (10/100/1000)
- IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
- Clause 45 MDIO PHY management
- Packet classifier based on ALE engine with 512 classifiers
- Priority-based flow control
- Time Sensitive Networking (TSN) support
- Four CPU H/W interrupt pacing
- IP/UDP/TCP checksum offload in hardware
- Two USB2.0 ports
- Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
- Integrated USB VBUS detection
- One Camera Serial interface (CSI-2) receiver with 4-lane D-PHY
- High-speed external processor data receive interface over CSI-2 and MIPI D-PHY
- Integrated Ethernet switch supporting (total of two external ports)
- General connectivity
- 9x Universal Asynchronous Receiver-Transmitters (UART)
- 5x Serial Peripheral Interface (SPI) controllers
- 6x Inter-Integrated Circuit (I2C) ports
- 3x Multichannel Audio Serial Ports (McASP)
- Transmit and Receive Clocks up to 50MHz
- Up to 4/6/16 serial data pins across 3x McASP with independent TX and RX clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and similar formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 formats)
- FIFO buffers for transmit and receive (256 Bytes)
- Support for audio reference output clock
- 3x enhanced PWM modules (ePWM)
- 3x enhanced Quadrature Encoder Pulse modules (eQEP)
- 3x enhanced Capture modules (eCAP)
- General-Purpose I/O (GPIO) with all LVCMOS I/O can be configured as GPIO
- 3x Controller Area Network (CAN) modules with CAN-FD support
- Conforms w/ CAN protocol 2.0 A, B, and ISO 11898-1
- Full CAN-FD support (up to 64 data bytes)
- Parity/ECC check for message RAM
- Speed up to 8Mbps
- Media and data storage
- 3x Multi-Media Card/Secure Digital® (MMC/SD®/SDIO) interface
- 1x 8-bit eMMC interface up to HS200 speed
- 2x 4-bit SD/SDIO interface up to UHS-I
- Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
- 1× General-Purpose Memory Controller (GPMC) up to 133MHz
- Flexible 8- and 16-bit asynchronous memory interface with up to four chip (22-bit address) selects (NAND, NOR, Muxed-NOR, and SRAM)
- Uses BCH code to support 4-, 8-, or 16-bit ECC
- Uses Hamming code to support 1-bit ECC
- Error Locator Module (ELM)
- Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
- Supports 4-, 8-, and 16-bit per 512-byte block error location based on BCH algorithms
- OSPI/QSPI with DDR / SDR support
- Support for serial NAND and serial NOR Flash devices
- 4GBytes memory address support
- XIP mode with optional on-the-fly encryption
- 3x Multi-Media Card/Secure Digital® (MMC/SD®/SDIO) interface
- Power management
- Low-power modes supported by the device/power manager
- Partial IO support for CAN/GPIO/UART wakeup
- Low-power modes supported by the device/power manager
- Boot options
- UART
- I2C EEPROM
- OSPI/QSPI Flash
- GPMC NOR/NAND Flash
- Serial NAND Flash
- SD Card
- eMMC
- USB (host) mass storage device
- USB (slave) boot from external host (DFU mode)
- Ethernet
- Technology/package
- 16nm FinFET technology
- 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)
Applications
- Automotive/premium audio amplifier
- Industrial/professional audio
- Aerospace and defense/radar and radio
- Marine equipment/sonar
- Medical and healthcare/ultrasound scanner
- Test and measurement/instrumentation
Functional Block Diagram
Development Tool
Texas Instruments TMDSEMU560V2STM-UE XDS560v2 System Trace
Debug probes that support both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
Publicado: 2025-07-07
| Actualizado: 2025-08-04